Registers based on flip flops are used in a variety of circuits for storing states. For reducing the current consumption of such a circuit, such circuit may comprise a Data Processing Mode in which the circuit performs its desired function. Furthermore, such devices or circuits may comprise a so-called Data Retention Mode or sleep or stand-by mode, in which the data processing of the device is interrupted. In the Data Retention Mode typically only a low static leakage current should be allowed. Furthermore, it is desired to ensure that after changing from the Data Retention Mode to the Data Processing Mode the device (e.g. the IC-integrated circuit) can immediately continue with the data processing. Furthermore, for a flip flop used in such a device the state stored in the flip flop should be preserved even in the Data Retention Mode.
Known concepts transfer data contents of registers to other storage circuits, for example, integrated register files or SRAM (static random access memory) of the IC before changing from the Data Processing Mode to the Data Retention Mode. These other storage circuits remain connected to the supply voltage in the Data Retention Mode. When resuming the Data Processing Mode these data contents are transferred back into the associated register. This concept has the disadvantage of additional circuitry and a significant increase in time and complexity.
Other concepts provide special Data Retention flip flops which comprise one additional low leakage latch (LLL) per bit to be saved. The stored information in the flip flop is transferred to this low leakage latch before entering the Data Retention Mode and is transferred back to the flip flop before resuming the Data Processing Mode. This enables, in the Data Retention Mode, the decoupling of the flip flop from the supply voltage, wherein the LLL is left coupled to the supply voltage. It can be achieved that the LLL consumes only small leakage current. This is possible because the LLL does not have to comply with any performance requirements. This concept has the disadvantage of a significant area and cost increase for the implementation of the low leakage latch.